In the integrated circuit (IC) industry, aluminum interconnects are now being replaced with copper-based inlaid interconnect structures. Copper interconnects are fairly new to the semiconductor industry and are very different from the more commonly used aluminum-based systems. For this reason, copper interconnects have uncovered new problems not before anticipated or addressed by integrated circuit manufacturing facilities. Specifically, a dual inlaid copper interconnect structure comprises at least two etch stop layers interleaved between at least two thicker silicon dioxide layers for a total of four layers of dielectric where aluminum usually required only one dielectric material made via one deposition step. The stack of at least two dielectric layers and at least two etch stop layers used by copper interconnects is lithographically patterned and etched in multiple photo steps and via multiple etch processes where aluminum interconnects generally need no such processing. Further the copper metallurgy itself usually requires multiple materials (e.g., barrier layers, seed layers, bulk layers, etc.), multiple deposition steps, and/or one or more chemical mechanical polishing (CMP) processes where aluminum processes needs only a single and simple deposition step.
In order to make these more complex copper interconnect structures efficiently and with high yield, engineers must consider many different combinations of complexities not before addressed. Specifically, lithographic and etch processing of dual inlaid copper structures must contend with one or more of: (1) adverse chemical interactions related to copper; (2) more complicated optical issues associated with the dielectric interfaces in the copper dielectric stack (e.g., light reflection, destructive interference, light distortion, etc.); (3) disadvantageous electrical properties associated with dielectric materials and etch stop layers within the copper dielectric stack; (4) complications in etch chemistries and etch processing; and (5) the more complicated mechanical integrity of the inlaid structure. While one of these five factors may have been faced by aluminum on occasion, never has a combination of two or more of these issues been a serious concern for aluminum-based ICs.
In addition to the collective weight of several of the five factors enumerated above, many copper-based designs require that different copper layers over the same integrated circuit have different trench depths and thicknesses. For example, the dual inlaid via height within inlaid structures may be designed to vary from layer to layer on the same IC, and different trench interconnect depths within the dual inlaid structures may also vary between the first metal layer and the Nth metal layer within a single integrated circuit (N being up to or greater than eight in current IC devices).
With respect to the first of the five factors enumerated above, integrated circuit engineers are concerned with adverse chemical interactions that are associated with copper based materials and processing. Copper will adversely react with ambient air and oxidize in a manner that could reduce integrated circuit yield and/or adversely increase the resistance of the electrical interconnects. In addition, all etch stops and/or capping layers in contact with the copper must be adequate diffusion barriers to prevent copper and associated impurities within the copper from diffusing through the film and contaminating adjacent dielectric layers or underlying electrical devices.
In addition to chemical reactions, engineers who are designing copper-based interconnects should also be concerned with the optical properties of the dielectric stack used to define a dual inlaid or inlaid structure. Chemically mechanically polished (CMP) copper has a highly reflective top surface which may readily reflect light/energy during lithographic operations. Furthermore, the plurality of dielectric layers in the dielectric stack of a copper interconnect creates many interfaces of different materials that can adversely reflect light and cause distortion of critical dimensions (CDs) and/or destructive interference whereby photoresist is not properly exposed and developed. In other words, at certain depths of lithographic focus, wavelengths of light, and thicknesses of material, light reflected from a surface of a copper interconnect or dielectric interfaces may destructively interfere or distort various lithographic feature sizes resulting in reduced yield and/or reduced performance of an integrated circuit. Therefore, various etch stop and capping layers within an inlaid copper structure should be geometrically and chemically designed with adequate anti-reflective coating (ARC) properties so that a high yield integrated circuit can be manufactured in an effective manner.
Specifically, the thicknesses of the dielectric and etch stop layers within the dielectric inlaid stack must be carefully engineered to reduce reflectance and/or ensure that any reflectance that occurs is primarily destructive interference when some level of reflection is unavoidable. In addition, the index of refraction (N) and the extinction coefficient (K) of the materials within the dielectric stack need to be carefully considered in order to tune the optical properties of the stack to the wavelength of lithographic light utilized. In addition, the interface between different materials within the dielectric stack must be carefully placed to avoid the various optical problems associated with unwanted reflection.
In addition to the chemical interaction concerns and optical concerns discussed above, various electrical properties of films within the dielectric stack must also be considered. Since the etch stop layers, ARC layers, and/or capping layers of the dielectric stack generally contact the interconnect metallurgy, the etch stop/ARC layers need to be materially engineered and physically placed within the dielectric stack to prevent unacceptable levels of leakage current between adjacent interconnects within an integrated circuit. In addition, the dielectric constants of these materials and/or the physical placement and cross sectional geometry of these materials need to be carefully engineered and considered in order to ensure that the IC may be operated at a high frequency of operation absent of significant cross talk and/or parasitic capacitance. In addition, the above engineering should strive to solve these problems while not to complicating the etch chemistries or the etch steps of the dielectric stack in a manner that is unacceptable.
The various layers contained within a dielectric stack of a dual inlaid copper interconnect create various mechanical concerns as well. The materials used in the dielectric stack must be engineered to provide adequate adhesion between silicon dioxide, copper, and various copper barrier materials. In addition, the stress exerted by these various films on the integrated circuit structure should be at or below an acceptable threshold. Further, the geometric aspect ratio of the via openings and the trench interconnect openings of the dual inlaid structure need to adjusted in order to ensure reduced keyhole formation, reduced voiding, and improved copper electromigration (EM) resistance.
A problem is that any one of the above concerns may be addressed and optimized within an IC interconnect structure when ignoring all the other concerns. When two or three, not to mention all five, of the above discussed concerns are considered at once, it is difficult to make the proper trade-offs and decisions that result in the best possible inlaid structure for a certain set of conditions.
Therefore, it should be evident to one of ordinary skill in the art that many complicated and sometimes conflicting concerns must be considered and balanced when engineering a multi-layer dielectric stack for use in copper interconnected devices. A structure that considers two or more of these needs and creates an improved inlaid structure is needed in the art.